1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device and more specifically to a method of manufacturing a semiconductor device including an element having a Metal-Insulator-Semiconductor structure such as a field effect transistor or the like.
2. Related Art
In order to appropriately operate a PMOS transistor and an NMOS transistor, it is necessary to control the threshold voltage of these transistors. Therefore, controls of work function or composition of the gate electrodes of the PMOS transistor and the NMOS transistor have been studied. Further, in order to avoid the depletion of the gate electrode, metal gates have been studied to be utilized. Among the metal gates, many studies have been conducted for Fully Silicided (FUSI) gate technique in which the gate electrode is fully silicided to an interface of a gate insulating film because of its adaptability to the conventional manufacturing process of the transistor.
In Japanese Laid-Open Patent Publication No. 2006-100431, a method of manufacturing a semiconductor device including a PMOS transistor and an NMOS transistor is disclosed. In this method, gate insulating films for the transistors are composed of silicon oxynitride (SiON) film and gate electrodes for the transistors are composed of poly-silicon, where boron is introduced into the gate electrode of the PMOS transistor and arsenic is introduced into the gate electrode of the NMOS transistor as impurities with use of resist masks. Then, Ni is formed over the gate electrodes for silicidation of the poly-silicon to have them fully silicided. By distributing the impurities into the interface between the gate insulating films and the FUSI gate electrodes, the work functions of the transistors are controlled.
It is disclosed in IEEE 2005 “Physical Mechanism of Work Function Modulation due to Impurity Pileup at Ni-FUSI/SiO(N) Interface”, that the composition or orientation of silicide phase depends on impurity which is introduced into the silicon before silicidation.
In IEDM 2004 “Dual Workfunction Ni-Silicide/HfSiON Gate Stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45 nm-node LSTP and LOP Devices” and Symposium on VLSI Technology Digest of Technical Papers 2005 “Highly Reliable HfSiON CMOSFET with Phase Controlled NiSi (NFET) and Ni3Si (PEET) FUSI Gate Electrode”, phase of the FUSI gate electrodes are appropriately controlled for the PMOS transistor and the NMOS transistor by changing Ni film thickness when forming the FUSI gate electrodes on HfSiON gate insulating films. With this structure, the threshold voltage of the CMOS can be appropriately controlled.
In Symposium on VLSI Technology Digest of Technical Papers 2006 “Dual work function phase controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe cap”, and IEEE 2005 “CMOS Integration of Dual Work Function Phase Controlled Ni FUSI with Simultaneous Silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) Gates on HfSiON”, the formation of FUSI electrodes having appropriate silicide phase by performing an etch back of the poly-silicon of the PMOS transistor to suppress the volume expansion at the time of forming Ni rich silicide. In these documents, impurity is not introduced into the gate electrodes and the composition of silicide phase is controlled by the thickness ratio of the Ni layer and the poly-silicon layer. In these documents, HfSiON is used as gate insulating films.
When manufacturing a device including a PMOS transistor and an NMOS transistor each having a FUSI gate electrode, the process flow will be complicated in order to appropriately control the composition of silicide phase of the gate electrodes, which are formed from poly-silicon, for both of the NMOS and PMOS transistors.